Chip fabrication involves the utilization of many processes that remove various layers from the silicon or other chip substrate. For example, an organic film, such as a resist or polyamide film temporarily formed on a substrate, which is a part of a semiconductor device, as a part of the process of fabricating the semiconductor device has in the past been removed by an ashing method using, for example an oxygen plasma. Removing the resist film is an important part of the process of fabricating a semiconductor device. Since the semiconductor industry is very small as compared to a Large Scale Integrated circuit device (LSI) or a Very Large Scale Integrated circuit device (VLSI) in which it is used, the resist film, which will be referred to as "resist" hereinafter, is hard to remove without damaging the device. Moreover, current chip fabrication requires extremely small size, so the feature size control is extremely tight. Thus, to avoid the infiltration of a particulate from chip processing, such as the ashing process, a technique is necessary to prevent the accumulation of a particulate in the resultant product.
U.S. Pat. No 5,104,482 discusses a glass deposition viscoelastic flow process for forming planar and semi-planar flow process for forming planar and semi-planar insulator structures on semiconductor devices, which comprises feeding vaporized reactants into a reaction chamber at a reaction temperature between 750 and 950 degrees Centigrade and subjecting the surface of the semiconductor devices to a high reactant velocity. The high reactant velocity allows the formation of a high quality, uniform glass layer at temperatures compatible with the fusion temperature, so that deposition occurs simultaneously with the viscoelastic flow of the glass. The simultaneous deposition and flow provides for topographical planarization substantially free of voids and other layer inconsistencies.
Other examples of current methods for manufacturing semiconductor devices include U.S. Pat. No. 5,540,811 to Toshiba which discloses a technique for providing a combination of layers of materials that have various properties that facilitate precise planarization of the substrate surfaces. In addition, on the basis of combinations of the selection of the polishing speed of the burying material and the optimization of the film thickness, it is possible to omit the processes of forming the block resist, the planarization resist and the etching process before polishing to simplify a manufacturing process. However, as with the aforedescribed plasma ashing process, the tolerances that this manufacturing technique provide are not adequate for modem VLSI devices.
Improved methods for manufacturing semiconductor devices have recently been developed, such as a photoresist strip method detailed in U.S. Pat. No. 5,792,672 to Chartered Semiconductor Manufacturing Ltd. The technique utilizes a two step process, in which a first stripping step is in a plasma containing oxygen and water, and a second stripping step is in a plasma containing oxygen.
Moreover, in a typical manufacturing process a large wafer of silicon, germanium or similar material in extremely pure crystalline form is overlayed sequentially with numerous layers of material which function as conductors, semiconductors or insulators. Each subsequent layer is deposited and patterned usually by photolithographic techniques such that the sequence of layers forms a complex array of electronic circuitry. However, the multiple layers can be formed only with diffficulty unless the substrate topography is planarized in an early stage of the manufacturing process and then maintained as closely as possible to a planar surface throughout subsequent layer depositions.
Generally, each device on the wafer is much smaller than the wafer itself. Once the wafer has been manufactured, one of the final steps in the manufacturing sequence is to cut the wafer into along predetermined scribe lines to many individual devices which are commonly referred to as "chips." However, because the chips are so small and their circuitry is so complex, almost any flaw or irregularity in a layer can disrupt the circuit patterns and render a given chip useless. Indeed it is fairly common for a substantial percentage of the chips on a wafer to be found defective upon testing. For example, using a prior art technique of film deposition followed by thermal fusion flow to planarize a glass layer can cause voids or other layer inconsistencies.
Thermal fusion flow, used as a generic term for glass flow or reflow is generally performed on the pre-metal dielectric passivation layers used in typical metal-oxide semiconductor (MOS) fabrication sequences. The flow is used to densify the glass layer and prepare it for a subsequent contact hole etch, and at the same time to improve its step coverage properties. The topography-smoothing measure is entended to ensure the continuity of the overlaying metallization as disclosed in Mercier, Rapid Flow of Doped Glasses for VLSIC Processing, Solid State Technology Vol. 30, No. 7, 85 (1987).
Although the use of a thermal fusion flow process is common in the prior art to obtain smooth or planarized successive layers, the likelihood of voids and other inconsistencies in the layers and the temperatures necessary to achieve the flow can foreclose the application of the thermal fusion flow process to heat sensitive VLSI devices.
The conventional method for BPSG processing consists of formation of the glass layer by Chemical Vapor Deposition (CVD). CVD processes operate on the basis of two surface reaction steps. First, one or more reactive gases, from which the compound or elements to be deposited will be obtained, are passed over the surface of the wafer under reaction conditions at which the wafer surface will catalyze the liberation of the deposited materials. In some cases the reactive gas will be introduced directly into the reactor, while in others it will be formed "in situ" in the gas space in the reactor by reaction from other introduced gases.
Ideally, it would be advantageous to have a deposition/planarization process that would create and deposit a glass film of varying composition by CVD and simultaneously with the deposition flow the layer as to completely fill, without voids, all spaces and trenches between the micron and sub-micron pattern features. This approach would eliminate the difficult requirement of substantially perfect conformality that must be attained by other methods of film deposition if planarization is to be accomplished to avoid the infiltration of a particulate.
Chemical Mechanical Processing (CMP) is widely used for manufacturing semiconductors. CMP is very effective for planarizing geometries that are not widely isolated. CMP processes planarize the surface of semiconductor wafers to a desired thickness. In a typical CMP process, a wafer attached to a carrier is pressed against a polishing pad in the presence of a slurry. The slurry contains abrasive particles that mechanically remove material from the wafer and chemicals that chemically treat the material that is ultimately polished. Waste material eventually accumulates on the planarizing surface of the polishing pad during planarization which diminishes the pads effectiveness. The waste matter on the pad reduces the effectiveness and the uniformity of the planarizing surface of the polishing pad. The waste matter accordingly reduces throughput of the CMP process and the uniformity of the polished surface on the wafer. Accordingly, it is necessary to periodically clean the planarizing surface of a polishing pad. Planarizing surfaces of polishing pads are conventionally cleaned by brushing the pad with a stiff brush, but U.S. Pat. No. 5,616,069 teaches a method of using a pad scrubber to clean the planarizing surface of a polishing pad used in CMP processing of semiconductor wafers. The pad scrubber has a fluid manifold and a plurality of nozzles coupled to the manifold to clean the pad as it is used in the CMP process. U.S. Pat. No. 5,816,891 discloses a method and apparatus for performing chemical mechanical polishing of oxides and metals using sequential removal on multiple polish platens to increase equipment throughput. U.S. Pat. No. 5,852,497 to the common assignee of this patent application discusses Shallow Trench Isolation (STI) for semiconductor manufacture wherein chemical mechanical polishing (CMP) is utilized to planarize the topography of the alignment marks. Because the polysilicon layer is opaque to the conventional white light source and the HeNe source, and because the alignment marks have been planarized, boundaries between different materials are used to form the alignment marks.
The present invention addresses the limitations of conventional CMP technology in achieving uniformly planarized surfaces of materials, particularly dielectric materials, at high removal rates. The inability of conventional CMP technology to achieve high polishing rates constitutes a serious economic impediment. Time consuming CMP decreases production throughput, consumes man hours and exhausts large amounts of cleaning agent and other consumable materials. The lack of a uniformly planarized surface adversely affects the reliability of the resulting semiconductor device, particularly in devices comprising multi-level vias wherein the upper vias would be overetched to insure complete etching at the lower levels.
U.S. Pat. No. 5,486,265 addresses and solves such limitations of conventional CMP technology, i.e., methodology and apparatus, by selecting an appropriate initial pressure applied to wafer undergoing CMP and intermittently reducing the initial pressure to a second pressure a plurality of times during the course of CMP processing. During the course of CMP processing, the surface to be polished in contact with the polishing pad becomes depleted in cleaning agent, which adversely affects the polishing rate and uniformity of the CMP operation, since incomplete polishing occurs in depleted areas, as toward the center of the wafer. By varying the pressure applied to the wafer undergoing CMP is intermittently reduced creating a pulsing pressure, thereby enabling the cleaning agent, which is normally continuously applied to the polishing pad, to continuously reach all portions of the surface of the wafer undergoing polishing throughout the entire CMP operation. Thus, the periodic reduction of pressure applied to the wafer during CMP processing eliminates the negative impact of starvation areas, i.e., areas which do not have a sufficient amount of cleaning agent. One limiting aspect of CMP is that the deposition of the layer being planarized generally has an effective distance over which gaps can be filled. These gaps can fill with a residue that adversely effects the resultant semiconductor.